4-mbit (256k x 16) pseudo static ram cyk256k16sccb cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05526 rev. *h revised october 18, 2006 features ? advanced low-power mobl ? architecture ? high speed: 55 ns, 60 ns and 70 ns ? wide voltage range: 2.7v to 3.3v ? typical active current: 1 ma @ f = 1 mhz ? low standby power ? automatic power-down when deselected functional description [1] the cyk256k16sccb is a high-performance cmos pseudo static ram (psram) organized as 256k words by 16 bits that supports an asynchronous memory interface. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life ? (mobl) in portable applications such as cellular telephones. the device can be put into standby mode reducing power consumption dramatically when deselected (ce 1 low, ce 2 high or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce 1 high, ce 2 low, oe is deasserted high), or during a write operation (chip enabled and write enable we low). reading from the device is accomplished by asserting the chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins a 0 through a 17 will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table for a complete description of read and write modes. note: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com. 256k x 16 ram array i/o 0 ?i/o 7 column decoder sense amps data in drivers oe i/o 8 ?i/o 15 we ble bhe row decoder power - down circuit bhe ble a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ce 2 ce 1 ce 2 ce 1 logic block diagram a 17 [+] feedback [+] feedback
cyk256k16sccb document #: 38-05526 rev. *h page 2 of 10 pin configuration [3, 4, 5] product portfolio product v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby, i sb2 ( a) f = 1 mhz f = f max min. typ. max. typ. [2] max. typ. [2] max. typ. [2] max. cyk256k16sccb 2.7 3.0 3.3 55 1 5 14 22 17 40 60 70 8 15 notes: 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ) and t a = 25c. 3. ball h1, g2, h6 are the address expansion pins fo r the 8-mb, 16-mb, and 32-mb densities, respectively. 4. nc ?no connect??not connect ed internally to the die. 5. dnu (do not use) pins have to be left floating or tied to v ss to ensure proper application. we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h a 16 dnu v cc 48-ball vfbga top view [+] feedback [+] feedback
cyk256k16sccb document #: 38-05526 rev. *h page 3 of 10 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied .............................................. ?40c to +85c supply voltage to ground potential ... ............. ? 0.4v to 4.6v dc voltage applied to outputs in high-z state [6, 7, 8] ....................................... ? 0.4v to 3.7v dc input voltage [6, 7, 8] .................................... ? 0.4v to 3.7v output current into outputs (low) ............................ 20 ma static discharge voltage ........ ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range range ambient temperature (t a )v cc industrial ? 25c to +85c 2.7v to 3.3v dc electrical characteristics (over the operating range) parameter description test conditions cyk256k16sccb -55, 60, 70 unit min. typ. [2] max. v cc supply voltage 2.7 3.0 3.3 v v oh output high voltage i oh = ? 0.1 ma v cc ? 0.4 v v ol output low voltage i ol = 0.1 ma 0.4 v v ih input high voltage 0.8 * v cc v cc + 0.4 v v il input low voltage f = 0 ? 0.4 0.62 v i ix input leakage current gnd < v in < vcc ? 1+1 a i oz output leakage current gnd < v out < vcc, output disabled ? 1+1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.3v, i out = 0 ma, cmos level 14 for ?55 14 for ?60 8 for ?70 22 for ?55 22 for ?60 15 for ?70 ma f = 1 mhz 1 for all speeds 5 for all speeds i sb1 automatic ce 1 power-down current ?cmos inputs ce > v cc ? 0.2v, ce 2 < 0.2v v in > v cc ? 0.2v, v in < 0.2v, f = f max (address and data only), f = 0 (oe , we , bhe and ble ) 150 250 a i sb2 automatic ce 1 power-down current ?cmos inputs ce > v cc ? 0.2v, ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.3v 17 40 a capacitance [9] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz v cc = v cc(typ) 8pf c out output capacitance 8 pf thermal resistance [9] parameter description test conditions vfbga unit ja thermal resistance (junction to ambient) test c onditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 55 c/w jc thermal resistance (jun ction to case) 17 c/w notes: 6. v ih(max) = v cc + 0.5v for pulse durations less than 20 ns. 7. v il(min) = ?0.5v for pulse durations less than 20 ns. 8. overshoot and undershoot spec ifications are characterized and are not 100% tested. 9. tested initially and after design or process changes that may affect these parameters. [+] feedback [+] feedback
cyk256k16sccb document #: 38-05526 rev. *h page 4 of 10 ac test loads and waveforms parameters 3.0v v cc unit r1 22000 ? r2 22000 ? r th 11000 ? v th 1.50 v switching characteristics (over the operating range) [10] parameter description ?55 ?60 ?70 unit min. max. min. max. min. max. read cycle t rc read cycle time 55 [14] 60 70 ns t aa address to data valid 55 60 70 ns t oha data hold from address change 5 8 10 ns t ace ce 1 low and ce 2 high to data valid 55 60 70 ns t doe oe low to data valid 25 25 35 ns t lzoe oe low to low z [11, 12] 555ns t hzoe oe high to high z [11, 12] 25 25 25 ns t lzce ce 1 low and ce 2 high to low z [11, 12] 555ns t hzce ce 1 high and ce 2 low to high z [11, 12] 25 25 25 ns t dbe ble /bhe low to data valid 55 60 70 ns t lzbe ble /bhe low to low z [11, 12] 555ns t hzbe ble /bhe high to high-z [11, 12] 10 10 25 ns t sk [14] address skew 0 5 10 ns write cycle [13] t wc write cycle time 55 60 70 ns t sce ce 1 low and ce 2 high to write end 45 45 60 ns t aw address set-up to write end 45 45 55 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns notes: 10. test conditions assume signal transition time of 1 v/ns or higher, timing reference levels of v cc(typ) /2, input pulse levels of 0v to v cc(typ), and output loading of the specified i ol /i oh and 30-pf load capacitance 11. t hzoe , t hzce , t hzbe and t hzwe transitions are measured when the outputs enter a high-impedance state. 12. high-z and low-z parameters are characterized and are not 100% tested. 13. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , ce 2 = v ih , bhe and/or ble =v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive . the data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. to achieve 55-ns performance, the read access should be ce controlled. in this case t ace is the critical parameter and t sk is satisfied when the addresses are stable prior to chip enable going active. for the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. vcc vcc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v th equivalent to: thevenin equivalent all input pulses r th r1 [+] feedback [+] feedback
cyk256k16sccb document #: 38-05526 rev. *h page 5 of 10 t pwe we pulse width 40 40 45 ns t bw ble /bhe low to write end 50 50 55 ns t sd data set-up to write end 25 25 25 ns t hd data hold from write end 0 0 0 ns t hzwe we low to high z [11, 12] 25 25 25 ns t lzwe we high to low z [11, 12] 555ns switching characteristics (over the operating range) [10] (continued) parameter description ?55 ?60 ?70 unit min. max. min. max. min. max. switching waveforms read cycle 1 (address transition controlled) [14, 15, 16] read cycle 2 (oe controlled) [14, 16] notes: 15. device is continuously selected. oe , ce = v il . 16. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha t sk data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe high oe ce 1 i cc impedanc e address ce 2 v cc t hzbe bhe / ble t lzbe t hzce data out t dbe t sk [+] feedback [+] feedback
cyk256k16sccb document #: 38-05526 rev. *h page 6 of 10 write cycle no. 1(we controlled) [12, 13, 17, 18, 19] notes: 17. data i/o is high impedance if oe > v ih . 18. if chip enable goes inactive simultaneously with we =high, the output remains in a high-impedance state. 19. during the don?t care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hz oe valid data ce 1 a dd ress ce 2 we datai/o oe bhe / ble t bw do n? t c ar e ce 2 [+] feedback [+] feedback
cyk256k16sccb document #: 38-05526 rev. *h page 7 of 10 write cycle 2 (ce 1 or ce 2 controlled) [12, 13, 17, 18, 19] write cycle 3 (we controlled, oe low) [18, 19] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data ce 1 address ce 2 we data i/o oe don?t care bhe /ble t bw t sa valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce 1 address ce 2 we data i/o t bw bhe / ble don?t care [+] feedback [+] feedback
cyk256k16sccb document #: 38-05526 rev. *h page 8 of 10 write cycle no. 4 (bhe /ble controlled, oe low) [18, 19] truth table [20] ce 1 ce 2 we oe bhe ble inputs/outputs mode power hxxxxxhigh z deselect/power-down standby (i sb ) x l x x x x high z deselect/power-down standby (i sb ) x x x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read (upper byte and lower byte) active (i cc ) lhhlhldata out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read (upper byte only) active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read (lower byte only) active (i cc ) l h h h l l high z output disabled active (i cc ) lhhhhlhigh z output disabled active (i cc ) l h h h l h high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write (upper byte and lower byte) active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write (lower byte only) active (i cc ) l h l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write (upper byte only) active (i cc ) switching waveforms (continued) data i /o a dd ress t hd t sd t sa t ha t aw t wc ce 1 we valid data tbw bh e /ble t sce ce 2 tpw e don?t care t hd note: 20. h = logic high, l = logic low, x = don?t care. [+] feedback [+] feedback
cyk256k16sccb document #: 38-05526 rev. *h page 9 of 10 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark, and mobl3 and more battery life are trademarks, of cypress semiconductor corporation. all product and company names mention ed in this document are the trademarks of their respective holders. ordering information speed (ns) ordering code package diagram package type operating range 55 cyk256k16sccbu-55bvi 51-85150 48-ball very fi ne pitch bga (6.0 x 8.0 x 1.0 mm) industrial CYK256K16SCBU-55BVXI 48-ball very fine pi tch bga (6.0 x 8.0 x 1.0 mm) (pb-free) 60 cyk256k16sccbu-60bvi 51-85150 48-ball very fi ne pitch bga (6.0 x 8.0 x 1.0 mm) industrial 70 cyk256k16sccbu-70bvi 51-85150 48-ball very fi ne pitch bga (6.0 x 8.0 x 1.0 mm) industrial cyk256k16scbu-70bvxi 48-ball very fine pi tch bga (6.0 x 8.0 x 1.0 mm) (pb-free) package diagram a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 48-ball vfbga (6 x 8 x 1 mm) (51-85150) 51-85150-*d [+] feedback [+] feedback
cyk256k16sccb document #: 38-05526 rev. *h page 10 of 10 document history page document title: cyk256k16sccb 4-mbit (256k x 16) pseudo static ram document number: 38-05526 rev. ecn no. issue date orig. of change description of change ** 215621 see ecn ref new data sheet *a 218183 see ecn ref changed ball e3 on package pinout from dnu to nc *b 230855 see ecn aju changed from advance information to preliminary modified max limit on dc input voltage in ?maximum ratings? section fixed package name typo in ?thermal resistance? table changed ordering code from cyk256k16sccb to cyk256k16sccbu in ?ordering information? section *c 234474 see ecn syt changed ball e3 on package pinout from nc to dnu. *d 260330 see ecn pci changed from preliminary to final *e 298651 see ecn pci added 60-ns speed bin *f 314013 see ecn rkf added pb-free parts to the ordering information *g 522566 see ecn nxr changed v il max spec from 0.4 v to 0.6 v in dc electrical characteristics table *h 562386 see ecn nxr changed v il max spec from 0.6 v to 0.62 v in dc electrical characteristics table [+] feedback [+] feedback
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